[drcachesim] Provide branch target for branch just prior to signal delivery

For #2638 (closed) we aided core simulation of drcachesim traces by guaranteeing that a branch's target immediately followed it and would not be interrupted by a thread switch.

But then in #3937 we allowed a signal to arrive after a branch, and removed the branch target guarantee for that case.

This issue covers addressing that lack of guarantee. DR did execute that branch, and after the signal it will go to the branch target rather than re-execute the branch instruction. Yet the core simulator doesn't know the branch target, especially for an indirect branch. It seems like we should figure out a solution here. Previously we discarded the idea of explicitly storing the branch target. Maybe we could insert the branch target as an instruction fetch entry that gets interrupted and re-executed post-signal (easiest to do this in the tracer as the post-processor will have a hard time finding the target, just like a core simulator).